Design Verification Engineer

ASIC Design Verificaion Engineer with experince n desigh-for-debug.





















The ideal candidate will use various verification techniques to achieve bug free first silicon SOC. Will utilize state of the art verification tools and golden reference models. Will be responsible for designing, integrating (3rd party) and maintaining test benches, writing and executing test plans, achieving code and functional coverage goals, random testing, regression, debug, and scripting. Experience with assertion based verification a plus.

ALL candidates must have 2 years beyond educational experience in a commercial environment.

Requirement:
- At least 4 years of hands-on experience.
- Good understanding of ASIC design and verification flow.
- Has successfully taped out an ASIC from test plan to sign off.
- Proficient in C/C++
- Proficient in Verilog
- Proficient in Perl or Shell scripting
- BSEE or equivalent

Candidates should also have experience in some of the following:
- Experience in PCI, Ethernet, USB, ATA, or OCP.
- Experience in Video (MPEG2, DVD, H.264) , Audio or Graphics
- SystemC, Specman e, Vera or SystemVerilog
- OVL, SVA, PSL, or 0-in
- VHDL
- MAKE
- Experience with HW/SW co-verification

Education:
BSEE/MSEE or equivalent. MS Preferred.